Build | OsvvmLibraries_RunAllTestsWithCoverage |
---|---|
Status | PASSED |
PASSED | 411 |
FAILED | 0 |
SKIPPED | 0 |
Analyze Failures | 0 |
Simulate Failures | 0 |
Elapsed Time (h:m:s) | 0:27:52 |
Elapsed Time (seconds) | 1672.318 |
Start Time | 2023-07-18T19:20-0700 |
Simulator | ActiveHDL |
Simulator Version | ActiveHDL-13.0.375.8320 |
OSVVM Version | 2023.07 |
Simulation Transcript | OsvvmLibraries_RunAllTestsWithCoverage.log |
HTML Simulation Transcript | OsvvmLibraries_RunAllTestsWithCoverage_log.html |
Code Coverage | Code Coverage Results |
Finish Time | 2023-07-18T19:47-0700 |
TestSuites | Status | PASSED | FAILED | SKIPPED | Requirements passed / goal |
Disabled Alerts |
Elapsed Time |
---|---|---|---|---|---|---|---|
StreamTransactionPkg | PASSED | 15 | 0 | 0 | 0 / 0 | 0 | 50.932 |
StreamTransactionArrayPkg | PASSED | 13 | 0 | 0 | 0 / 0 | 0 | 44.886 |
AddressBusTransactionPkg | PASSED | 42 | 0 | 0 | 0 / 0 | 0 | 158.896 |
AddressBusTransactionArrayPkg | PASSED | 42 | 0 | 0 | 0 / 0 | 0 | 155.650 |
InterruptHandler_Gen | PASSED | 6 | 0 | 0 | 0 / 0 | 0 | 24.108 |
Axi4Lite | PASSED | 11 | 0 | 0 | 0 / 0 | 0 | 42.584 |
Axi4Full | PASSED | 68 | 0 | 0 | 0 / 0 | 0 | 266.224 |
AxiStream | PASSED | 65 | 0 | 0 | 0 / 0 | 0 | 231.806 |
Uart | PASSED | 9 | 0 | 0 | 0 / 0 | 0 | 47.669 |
DpRam | PASSED | 1 | 0 | 0 | 0 / 0 | 0 | 13.592 |
Ethernet | PASSED | 6 | 0 | 0 | 0 / 0 | 0 | 21.854 |
Axi4Full_VTI | PASSED | 68 | 0 | 0 | 0 / 0 | 0 | 270.266 |
AxiStream_VTI | PASSED | 65 | 0 | 0 | 0 / 0 | 0 | 252.278 |
Test Case | Status | Checks | Requirements | Functional Coverage |
Disabled Alerts |
Elapsed Time |
|||
---|---|---|---|---|---|---|---|---|---|
Total | Passed | Failed | Goal | Passed | |||||
TbStream_SendGet1 | PASSED | 1296 | 1294 | 0 | 0 | 0 | 100.00 | 0 | 3.165 |
TbStream_SendGetAsync1 | PASSED | 1296 | 1294 | 0 | 0 | 0 | 100.00 | 0 | 1.682 |
TbStream_SendGetAll1 | PASSED | 249 | 249 | 0 | 0 | 0 | 100.00 | 0 | 2.241 |
TbStream_SendGetAllAsync1 | PASSED | 249 | 249 | 0 | 0 | 0 | 100.00 | 0 | 1.909 |
TbAxi_SendGetAllParam1 | PASSED | 282 | 282 | 0 | 0 | 0 | 100.00 | 0 | 1.581 |
TbAxi_SendGetAllParamAsync1 | PASSED | 282 | 282 | 0 | 0 | 0 | 100.00 | 0 | 1.810 |
TbStream_GotBurst1 | PASSED | 74 | 74 | 0 | 0 | 0 | 100.00 | 0 | 1.549 |
TbStream_SendCheckBurstVector1 | PASSED | 66 | 66 | 0 | 0 | 0 | 100.00 | 0 | 1.549 |
TbStream_SendCheckBurstVectorAsync1 | PASSED | 52 | 52 | 0 | 0 | 0 | 100.00 | 0 | 2.501 |
TbStream_ReleaseAcquireTransmitter1 | PASSED | 34 | 34 | 0 | 0 | 0 | 100.00 | 0 | 1.848 |
TbStream_ReleaseAcquireReceiver1 | PASSED | 36 | 36 | 0 | 0 | 0 | 100.00 | 0 | 1.305 |
TbStream_MultipleDriversTransmitter1 | PASSED | 0 | 0 | 0 | 0 | 0 | 100.00 | 0 | 1.575 |
TbStream_MultipleDriversReceiver1 | PASSED | 0 | 0 | 0 | 0 | 0 | 100.00 | 0 | 1.345 |
TbAxi_SetBurstMode1 | PASSED | 6 | 6 | 0 | 0 | 0 | 100.00 | 0 | 1.588 |
TbAxi_SetModelOptions1 | PASSED | 6 | 6 | 0 | 0 | 0 | 100.00 | 0 | 1.968 |
Test Case | Status | Checks | Requirements | Functional Coverage |
Disabled Alerts |
Elapsed Time |
|||
---|---|---|---|---|---|---|---|---|---|
Total | Passed | Failed | Goal | Passed | |||||
TbStream_SendGet1 | PASSED | 1296 | 1294 | 0 | 0 | 0 | 100.00 | 0 | 1.882 |
TbStream_SendGetAsync1 | PASSED | 1296 | 1294 | 0 | 0 | 0 | 100.00 | 0 | 1.463 |
TbStream_SendGetAll1 | PASSED | 249 | 249 | 0 | 0 | 0 | 100.00 | 0 | 1.732 |
TbStream_SendGetAllAsync1 | PASSED | 249 | 249 | 0 | 0 | 0 | 100.00 | 0 | 2.003 |
TbAxi_SendGetAllParam1 | PASSED | 282 | 282 | 0 | 0 | 0 | 100.00 | 0 | 2.102 |
TbAxi_SendGetAllParamAsync1 | PASSED | 282 | 282 | 0 | 0 | 0 | 100.00 | 0 | 2.161 |
TbStream_GotBurst1 | PASSED | 74 | 74 | 0 | 0 | 0 | 100.00 | 0 | 1.601 |
TbStream_ReleaseAcquireTransmitter1 | PASSED | 34 | 34 | 0 | 0 | 0 | 100.00 | 0 | 1.418 |
TbStream_ReleaseAcquireReceiver1 | PASSED | 36 | 36 | 0 | 0 | 0 | 100.00 | 0 | 1.326 |
TbStream_MultipleDriversTransmitter1 | PASSED | 0 | 0 | 0 | 0 | 0 | 100.00 | 0 | 1.854 |
TbStream_MultipleDriversReceiver1 | PASSED | 0 | 0 | 0 | 0 | 0 | 100.00 | 0 | 2.114 |
TbAxi_SetBurstMode1 | PASSED | 6 | 6 | 0 | 0 | 0 | 100.00 | 0 | 1.815 |
TbAxi_SetModelOptions1 | PASSED | 6 | 6 | 0 | 0 | 0 | 100.00 | 0 | 1.732 |
Test Case | Status | Checks | Requirements | Functional Coverage |
Disabled Alerts |
Elapsed Time |
|||
---|---|---|---|---|---|---|---|---|---|
Total | Passed | Failed | Goal | Passed | |||||
TbAb_Interrupt1 | PASSED | 96 | 96 | 0 | 0 | 0 | 100.00 | 0 | 2.508 |
TbAb_Interrupt2 | PASSED | 240 | 240 | 0 | 0 | 0 | 100.00 | 0 | 2.965 |
TbAb_Interrupt3 (2) | PASSED | 240 | 240 | 0 | 0 | 0 | 100.00 | 0 | 2.028 |
TbAb_InterruptBurst1 | PASSED | 72 | 72 | 0 | 0 | 0 | 100.00 | 0 | 1.798 |
TbAb_InterruptBurst2 | PASSED | 216 | 216 | 0 | 0 | 0 | 100.00 | 0 | 1.760 |
TbAb_InterruptNoHandler1 | PASSED | 96 | 96 | 0 | 0 | 0 | 100.00 | 0 | 1.939 |
Test Case | Status | Checks | Requirements | Functional Coverage |
Disabled Alerts |
Elapsed Time |
|||
---|---|---|---|---|---|---|---|---|---|
Total | Passed | Failed | Goal | Passed | |||||
TbAxi4_BasicReadWrite | PASSED | 60 | 60 | 0 | 0 | 0 | - | 0 | 1.936 |
TbAxi4_ReadWriteAsync1 | PASSED | 60 | 60 | 0 | 0 | 0 | - | 0 | 1.761 |
TbAxi4_ReadWriteAsync2 | PASSED | 60 | 60 | 0 | 0 | 0 | - | 0 | 1.846 |
TbAxi4_ReadWriteAsync3 | PASSED | 60 | 60 | 0 | 0 | 0 | - | 0 | 1.622 |
TbAxi4_RandomReadWrite | PASSED | 3000 | 3000 | 0 | 0 | 0 | - | 0 | 3.124 |
TbAxi4_RandomReadWriteByte | PASSED | 3000 | 3000 | 0 | 0 | 0 | - | 0 | 2.274 |
TbAxi4_TimeOut | PASSED | 75 | 71 | 0 | 0 | 0 | - | 0 | 1.670 |
TbAxi4_WriteOptions | PASSED | 72 | 72 | 0 | 0 | 0 | - | 0 | 1.420 |
TbAxi4_MemoryReadWrite1 | PASSED | 40 | 40 | 0 | 0 | 0 | - | 0 | 1.836 |
TbAxi4_AxiXResp | PASSED | 36 | 36 | 0 | 0 | 0 | - | 0 | 1.876 |
TbAxi4_AxiXResp2_Enum | PASSED | 36 | 36 | 0 | 0 | 0 | - | 0 | 2.280 |
Test Case | Status | Checks | Requirements | Functional Coverage |
Disabled Alerts |
Elapsed Time |
|||
---|---|---|---|---|---|---|---|---|---|
Total | Passed | Failed | Goal | Passed | |||||
TbUart_SendGet1 | PASSED | 34 | 30 | 0 | 0 | 0 | - | 0 | 2.986 |
TbUart_SendGet2 | PASSED | 26 | 22 | 0 | 0 | 0 | - | 0 | 2.241 |
TbUart_Options1 | PASSED | 125 | 125 | 0 | 0 | 0 | - | 0 | 1.878 |
TbUart_Options2 | PASSED | 12 | 12 | 0 | 0 | 0 | - | 0 | 1.803 |
TbUart_Checkers1 | PASSED | 26 | 11 | 0 | 0 | 0 | - | 0 | 2.146 |
TbUart_Checkers2 | PASSED | 26 | 11 | 0 | 0 | 0 | - | 0 | 1.919 |
TbUart_Scoreboard1 | PASSED | 140 | 48 | 0 | 0 | 0 | - | 0 | 4.778 |
TbUart_Overload1 | PASSED | 34 | 30 | 0 | 0 | 0 | - | 0 | 1.947 |
TbUart_SingleProcess_1 | PASSED | 16 | 16 | 0 | 0 | 0 | - | 0 | 2.365 |
Test Case | Status | Checks | Requirements | Functional Coverage |
Disabled Alerts |
Elapsed Time |
|||
---|---|---|---|---|---|---|---|---|---|
Total | Passed | Failed | Goal | Passed | |||||
TbDpRam_BasicReadWrite | PASSED | 40 | 40 | 0 | 0 | 0 | - | 0 | 2.123 |
Test Case | Status | Checks | Requirements | Functional Coverage |
Disabled Alerts |
Elapsed Time |
|||
---|---|---|---|---|---|---|---|---|---|
Total | Passed | Failed | Goal | Passed | |||||
Tb_xMii1 | PASSED | 2065 | 2065 | 0 | 0 | 0 | - | 0 | 2.693 |
Tb_xMii1 (RGMII ,BPS_1G) | PASSED | 2065 | 2065 | 0 | 0 | 0 | - | 0 | 1.883 |
Tb_xMii1 (MII ,BPS_100M) | PASSED | 2065 | 2065 | 0 | 0 | 0 | - | 0 | 2.209 |
Tb_xMii1 (MII ,BPS_10M) | PASSED | 2065 | 2065 | 0 | 0 | 0 | - | 0 | 2.684 |
Tb_xMii1 (RMII ,BPS_100M) | PASSED | 2065 | 2065 | 0 | 0 | 0 | - | 0 | 2.150 |
Tb_xMii1 (RMII ,BPS_10M) | PASSED | 2065 | 2065 | 0 | 0 | 0 | - | 0 | 2.251 |