| Available Reports |
|---|
| Alert Report |
| Functional Coverage Report(s) |
| ScoreboardPkg_slv Report(s) |
| Link to Simulation Results |
| TbAxi4_AlertLogIDMemory.txt |
| OsvvmLibraries_RunAllTestsWithCoverage Build Summary |
TbAxi4_AlertLogIDMemory Alert Report
TbAxi4_AlertLogIDMemory Alert Settings
| Setting | Value | Description | |
|---|---|---|---|
| FailOnWarning | true | If true, warnings are a test error | |
| FailOnDisabledErrors | true | If true, Disabled Alert Counts are a test error | |
| FailOnRequirementErrors | true | If true, Requirements Errors are a test error | |
| External | Failures | 0 | Added to Alert Counts in determine total errors |
| Errors | 0 | ||
| Warnings | 0 | ||
| Expected | Failures | 1 | Subtracted from Alert Counts in determine total errors |
| Errors | 1 | ||
| Warnings | 1 | ||
TbAxi4_AlertLogIDMemory Alert Results
| Name | Status | Checks | Requirements | Alert Counts | Disabled Alert Counts | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Total | Passed | Failed | Goal | Passed | Failures | Errors | Warnings | Failures | Errors | Warnings | ||
| TbAxi4_AlertLogIDMemory | PASSED | 8 | 8 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 |
| Default | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| OSVVM | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| memory_1 | FAILED | 0 | 0 | 3 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 |
| memory_1:memory | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Data Check | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteBurstFifo | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadBurstFifo | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| interrupthandler_1 | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteBurstFifo | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadBurstFifo | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| manager_1 | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Protocol Error | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Data Check | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteResponse Scoreboard | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadResponse Scoreboard | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteBurstFifo | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadBurstFifo | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Manager | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Subordinate | PASSED | 8 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
TbAxi4_AlertLogIDMemory Coverage Report
Total Coverage: 100.00
WriteAddressDelayCov BurstLength Coverage Model Coverage: 0.0
WriteAddressDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 725712538, 1004918336 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteAddressDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteAddressDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteAddressDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1827999928, 1437906479 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteAddressDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
WriteAddressDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteAddressDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 734265393, 1700735930 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteAddressDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
WriteDataDelayCov BurstLength Coverage Model Coverage: 0.0
WriteDataDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 2029461548, 1283764278 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteDataDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteDataDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteDataDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1748909411, 1855022683 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteDataDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
WriteDataDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteDataDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 96983514, 129940445 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteDataDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
WriteResponseDelayCov BurstLength Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 725712538, 1828020551 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteResponseDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteResponseDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 168568802, 1013319321 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteResponseDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteResponseDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 734265393, 1132220686 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteResponseDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadAddressDelayCov BurstLength Coverage Model Coverage: 0.0
ReadAddressDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 348462515, 977886568 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadAddressDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadAddressDelayCov BurstDelay Coverage Model Coverage: 0.0
ReadAddressDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1827999928, 403794932 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadAddressDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
ReadAddressDelayCov BeatDelay Coverage Model Coverage: 0.0
ReadAddressDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 999833807, 1972030371 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadAddressDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
ReadDataDelayCov BurstLength Coverage Model Coverage: 0.0
ReadDataDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 2029461548, 1245869864 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadDataDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadDataDelayCov BurstDelay Coverage Model Coverage: 0.0
ReadDataDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 900544662, 1715637110 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadDataDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadDataDelayCov BeatDelay Coverage Model Coverage: 0.0
ReadDataDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 96983514, 1534593060 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadDataDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteAddressDelayCov BurstLength Coverage Model Coverage: 0.0
WriteAddressDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1296437502, 1511131805 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteAddressDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteAddressDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteAddressDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 628491352, 1843851328 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteAddressDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteAddressDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteAddressDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 963124330, 867366020 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteAddressDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteDataDelayCov BurstLength Coverage Model Coverage: 0.0
WriteDataDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1992752071, 1456192725 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteDataDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteDataDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteDataDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1940533339, 2055473551 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteDataDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteDataDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteDataDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1136972191, 1113371690 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteDataDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteResponseDelayCov BurstLength Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1935614252, 1231610140 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteResponseDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteResponseDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 628491352, 1519532790 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteResponseDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
WriteResponseDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1682240380, 1538165535 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
WriteResponseDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
ReadAddressDelayCov BurstLength Coverage Model Coverage: 0.0
ReadAddressDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1296437502, 1383831417 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadAddressDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadAddressDelayCov BurstDelay Coverage Model Coverage: 0.0
ReadAddressDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1712199934, 1717908421 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadAddressDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadAddressDelayCov BeatDelay Coverage Model Coverage: 0.0
ReadAddressDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 963124330, 2144458818 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadAddressDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadDataDelayCov BurstLength Coverage Model Coverage: 0.0
ReadDataDelayCov BurstLength Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1362522746, 1446320732 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadDataDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadDataDelayCov BurstDelay Coverage Model Coverage: 0.0
ReadDataDelayCov BurstDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 1940533339, 551584956 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadDataDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
ReadDataDelayCov BeatDelay Coverage Model Coverage: 0.0
ReadDataDelayCov BeatDelay Coverage Settings
| Settings | Value |
|---|---|
| CovWeight | 0 |
| Goal | 100.0 |
| WeightMode | REMAIN |
| Seeds | 2118121841, 781495195 |
| CountMode | COUNT_FIRST |
| IllegalMode | ILLEGAL_ON |
| Threshold | 45.0 |
| ThresholdEnable | FALSE |
| TotalCovCount | 0 |
| TotalCovGoal | 1 |
ReadDataDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
TbAxi4_AlertLogIDMemory Scoreboard Report for Scoreboard_slv
| Name | ParentName | ItemCount | ErrorCount | ItemsChecked | ItemsPopped | ItemsDropped | FifoCount |
|---|---|---|---|---|---|---|---|
| WriteAddressFIFO | memory_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteDataFifo | memory_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteResponseFifo | memory_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadAddressFifo | memory_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadDataFifo | memory_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteResponse Scoreboard | manager_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadResponse Scoreboard | manager_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteAddressFIFO | manager_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteDataFifo | manager_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadAddressFifo | manager_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadAddressTransactionFifo | manager_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadDataFifo | manager_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteBurstFifo | memory_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadBurstFifo | memory_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteBurstFifo | manager_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadBurstFifo | manager_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| WriteBurstFifo | interrupthandler_1 | 0 | 0 | 0 | 0 | 0 | 0 |
| ReadBurstFifo | interrupthandler_1 | 0 | 0 | 0 | 0 | 0 | 0 |