 
    TbAxi4_SubordinateRandomTiming1 Alert Report
TbAxi4_SubordinateRandomTiming1 Alert Settings
| Setting | Value | Description | |
|---|---|---|---|
| FailOnWarning | true | If true, warnings are a test error | |
| FailOnDisabledErrors | true | If true, Disabled Alert Counts are a test error | |
| FailOnRequirementErrors | true | If true, Requirements Errors are a test error | |
| External | Failures | 0 | Added to Alert Counts in determine total errors | 
| Errors | 0 | ||
| Warnings | 0 | ||
| Expected | Failures | 0 | Subtracted from Alert Counts in determine total errors | 
| Errors | 0 | ||
| Warnings | 0 | ||
TbAxi4_SubordinateRandomTiming1 Alert Results
| Name | Status | Checks | Requirements | Alert Counts | Disabled Alert Counts | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Total | Passed | Failed | Goal | Passed | Failures | Errors | Warnings | Failures | Errors | Warnings | ||
| TbAxi4_SubordinateRandomTiming1 | PASSED | 768 | 768 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| Default | PASSED | 384 | 384 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| OSVVM | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| subordinate_1 | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| Protocol Error | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| Data Check | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| manager_1 | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| Protocol Error | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| Data Check | PASSED | 128 | 128 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| WriteResponse Scoreboard | PASSED | 128 | 128 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
| ReadResponse Scoreboard | PASSED | 128 | 128 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 
TbAxi4_SubordinateRandomTiming1 Coverage Report
Total Coverage: 100.00
WriteAddressDelayCov BurstLength Coverage Model Coverage: 100.0
WriteAddressDelayCov BurstLength Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1780638781, 1284630316 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
WriteAddressDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 4 | 43 | 1 | 4300.0 | |
| Total Percent Coverage: 100.0 | |||||
WriteAddressDelayCov BurstDelay Coverage Model Coverage: 100.0
WriteAddressDelayCov BurstDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 2072006919, 359507871 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
WriteAddressDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 43 | 1 | 4300.0 | |
| Total Percent Coverage: 100.0 | ||||||
WriteAddressDelayCov BeatDelay Coverage Model Coverage: 100.0
WriteAddressDelayCov BeatDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1210226302, 1715992792 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
WriteAddressDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 86 | 1 | 8600.0 | |
| Total Percent Coverage: 100.0 | ||||||
WriteDataDelayCov BurstLength Coverage Model Coverage: 100.0
WriteDataDelayCov BurstLength Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 276880993, 492374260 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
WriteDataDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 22 | 1 | 2200.0 | |
| Total Percent Coverage: 100.0 | |||||
WriteDataDelayCov BurstDelay Coverage Model Coverage: 100.0
WriteDataDelayCov BurstDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1798108825, 1316270049 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
WriteDataDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 22 | 1 | 2200.0 | |
| Total Percent Coverage: 100.0 | ||||||
WriteDataDelayCov BeatDelay Coverage Model Coverage: 100.0
WriteDataDelayCov BeatDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1132275268, 1747695844 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
WriteDataDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 107 | 1 | 10700.0 | |
| Total Percent Coverage: 100.0 | ||||||
WriteResponseDelayCov BurstLength Coverage Model Coverage: 100.0
WriteResponseDelayCov BurstLength Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1157222341, 2137987343 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
WriteResponseDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 23 | 1 | 2300.0 | |
| Total Percent Coverage: 100.0 | |||||
WriteResponseDelayCov BurstDelay Coverage Model Coverage: 100.0
WriteResponseDelayCov BurstDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1774513708, 1565671199 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
WriteResponseDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 23 | 1 | 2300.0 | |
| Total Percent Coverage: 100.0 | |||||
WriteResponseDelayCov BeatDelay Coverage Model Coverage: 100.0
WriteResponseDelayCov BeatDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1521444320, 1618564945 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
WriteResponseDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 0 | 105 | 1 | 10500.0 | |
| Total Percent Coverage: 100.0 | |||||
ReadAddressDelayCov BurstLength Coverage Model Coverage: 100.0
ReadAddressDelayCov BurstLength Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 341347771, 916637069 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
ReadAddressDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 4 | 45 | 1 | 4500.0 | |
| Total Percent Coverage: 100.0 | |||||
ReadAddressDelayCov BurstDelay Coverage Model Coverage: 100.0
ReadAddressDelayCov BurstDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1157257181, 106345226 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
ReadAddressDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 45 | 1 | 4500.0 | |
| Total Percent Coverage: 100.0 | ||||||
ReadAddressDelayCov BeatDelay Coverage Model Coverage: 100.0
ReadAddressDelayCov BeatDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 176887009, 1625770513 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
ReadAddressDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 84 | 1 | 8400.0 | |
| Total Percent Coverage: 100.0 | ||||||
ReadDataDelayCov BurstLength Coverage Model Coverage: 100.0
ReadDataDelayCov BurstLength Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1227410821, 1030023635 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
ReadDataDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 21 | 1 | 2100.0 | |
| Total Percent Coverage: 100.0 | |||||
ReadDataDelayCov BurstDelay Coverage Model Coverage: 100.0
ReadDataDelayCov BurstDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1603737730, 733523584 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
ReadDataDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 21 | 1 | 2100.0 | |
| Total Percent Coverage: 100.0 | |||||
ReadDataDelayCov BeatDelay Coverage Model Coverage: 100.0
ReadDataDelayCov BeatDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 422304604, 1892012361 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 1 | 
| TotalCovGoal | 1 | 
ReadDataDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 0 | 107 | 1 | 10700.0 | |
| Total Percent Coverage: 100.0 | |||||
WriteAddressDelayCov BurstLength Coverage Model Coverage: 0.0
WriteAddressDelayCov BurstLength Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1296437502, 1511131805 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
WriteAddressDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteAddressDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteAddressDelayCov BurstDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 628491352, 1843851328 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
WriteAddressDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteAddressDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteAddressDelayCov BeatDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 963124330, 867366020 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
WriteAddressDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteDataDelayCov BurstLength Coverage Model Coverage: 0.0
WriteDataDelayCov BurstLength Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1992752071, 1456192725 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
WriteDataDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteDataDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteDataDelayCov BurstDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1940533339, 2055473551 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
WriteDataDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteDataDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteDataDelayCov BeatDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1136972191, 1113371690 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
WriteDataDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteResponseDelayCov BurstLength Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstLength Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1935614252, 1231610140 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
WriteResponseDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
WriteResponseDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 628491352, 1519532790 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
WriteResponseDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
WriteResponseDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BeatDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1682240380, 1538165535 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
WriteResponseDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
ReadAddressDelayCov BurstLength Coverage Model Coverage: 0.0
ReadAddressDelayCov BurstLength Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1296437502, 1383831417 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
ReadAddressDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadAddressDelayCov BurstDelay Coverage Model Coverage: 0.0
ReadAddressDelayCov BurstDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1712199934, 1717908421 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
ReadAddressDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadAddressDelayCov BeatDelay Coverage Model Coverage: 0.0
ReadAddressDelayCov BeatDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 963124330, 2144458818 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
ReadAddressDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadDataDelayCov BurstLength Coverage Model Coverage: 0.0
ReadDataDelayCov BurstLength Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1362522746, 1446320732 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
ReadDataDelayCov BurstLength Coverage Bins
| Name | Type | Bin1 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|
| COUNT | 2 to 10 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | |||||
ReadDataDelayCov BurstDelay Coverage Model Coverage: 0.0
ReadDataDelayCov BurstDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 1940533339, 551584956 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
ReadDataDelayCov BurstDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|---|
| COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
ReadDataDelayCov BeatDelay Coverage Model Coverage: 0.0
ReadDataDelayCov BeatDelay Coverage Settings
| Settings | Value | 
|---|---|
| CovWeight | 0 | 
| Goal | 100.0 | 
| WeightMode | REMAIN | 
| Seeds | 2118121841, 781495195 | 
| CountMode | COUNT_FIRST | 
| IllegalMode | ILLEGAL_ON | 
| Threshold | 45.0 | 
| ThresholdEnable | FALSE | 
| TotalCovCount | 0 | 
| TotalCovGoal | 1 | 
ReadDataDelayCov BeatDelay Coverage Bins
| Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage | 
|---|---|---|---|---|---|---|
| COUNT | 0 | 0 | 0 | 1 | 0.0 | |
| Total Percent Coverage: 0.0 | ||||||
TbAxi4_SubordinateRandomTiming1 Scoreboard Report for Scoreboard_slv
| Name | ParentName | ItemCount | ErrorCount | ItemsChecked | ItemsPopped | ItemsDropped | FifoCount | 
|---|---|---|---|---|---|---|---|
| WriteAddressFIFO | subordinate_1 | 128 | 0 | 0 | 128 | 0 | 0 | 
| WriteDataFifo | subordinate_1 | 128 | 0 | 0 | 128 | 0 | 0 | 
| WriteTransactionFifo | subordinate_1 | 0 | 0 | 0 | 0 | 0 | 0 | 
| WriteResponseFifo | subordinate_1 | 128 | 0 | 0 | 128 | 0 | 0 | 
| ReadAddressFifo | subordinate_1 | 128 | 0 | 0 | 128 | 0 | 0 | 
| ReadAddressTransactionFifo | subordinate_1 | 128 | 0 | 0 | 128 | 0 | 0 | 
| ReadDataFifo | subordinate_1 | 128 | 0 | 0 | 128 | 0 | 0 | 
| WriteResponse Scoreboard | manager_1 | 128 | 0 | 128 | 128 | 0 | 0 | 
| ReadResponse Scoreboard | manager_1 | 128 | 0 | 128 | 128 | 0 | 0 | 
| WriteAddressFIFO | manager_1 | 128 | 0 | 0 | 128 | 0 | 0 | 
| WriteDataFifo | manager_1 | 128 | 0 | 0 | 128 | 0 | 0 | 
| ReadAddressFifo | manager_1 | 128 | 0 | 0 | 128 | 0 | 0 | 
| ReadAddressTransactionFifo | manager_1 | 128 | 0 | 0 | 128 | 0 | 0 | 
| ReadDataFifo | manager_1 | 128 | 0 | 0 | 128 | 0 | 0 |