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TbAxi4_ManagerRandomTiming1 Alert Report
TbAxi4_ManagerRandomTiming1 Alert Settings
Setting | Value | Description | |
---|---|---|---|
FailOnWarning | true | If true, warnings are a test error | |
FailOnDisabledErrors | true | If true, Disabled Alert Counts are a test error | |
FailOnRequirementErrors | true | If true, Requirements Errors are a test error | |
External | Failures | 0 | Added to Alert Counts in determine total errors |
Errors | 0 | ||
Warnings | 0 | ||
Expected | Failures | 0 | Subtracted from Alert Counts in determine total errors |
Errors | 0 | ||
Warnings | 0 |
TbAxi4_ManagerRandomTiming1 Alert Results
Name | Status | Checks | Requirements | Alert Counts | Disabled Alert Counts | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Total | Passed | Failed | Goal | Passed | Failures | Errors | Warnings | Failures | Errors | Warnings | ||
TbAxi4_ManagerRandomTiming1 | PASSED | 480 | 480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Default | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
OSVVM | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
subordinate_1 | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
:tbaxi4memory:subordinate_1::memory | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Data Check | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
manager_1 | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Protocol Error | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Data Check | PASSED | 160 | 160 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
WriteResponse Scoreboard | PASSED | 160 | 160 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
ReadResponse Scoreboard | PASSED | 160 | 160 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
TbAxi4_ManagerRandomTiming1 Coverage Report
Total Coverage: 100.00
WriteAddressDelayCov BurstLength Coverage Model Coverage: 0.0
WriteAddressDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 201959419, 353797856 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteAddressDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteAddressDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteAddressDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 779970012, 1610791482 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteAddressDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteAddressDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteAddressDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1367125401, 794307227 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteAddressDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 | 0 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteDataDelayCov BurstLength Coverage Model Coverage: 0.0
WriteDataDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 332594846, 475700727 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteDataDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteDataDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteDataDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1603832055, 1829461270 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteDataDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteDataDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteDataDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1603111803, 325466259 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteDataDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 | 0 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteResponseDelayCov BurstLength Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 216688206, 1846275625 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteResponseDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteResponseDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 779970012, 367264995 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteResponseDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 5 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteResponseDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 2123892427, 1305105689 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteResponseDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 0 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
ReadAddressDelayCov BurstLength Coverage Model Coverage: 0.0
ReadAddressDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 201959419, 1150771571 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
ReadAddressDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
ReadAddressDelayCov BurstDelay Coverage Model Coverage: 0.0
ReadAddressDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1391413899, 1644849628 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
ReadAddressDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
ReadAddressDelayCov BeatDelay Coverage Model Coverage: 0.0
ReadAddressDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1367125401, 1163966820 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
ReadAddressDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 | 0 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
ReadDataDelayCov BurstLength Coverage Model Coverage: 0.0
ReadDataDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1832458720, 1220308451 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
ReadDataDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
ReadDataDelayCov BurstDelay Coverage Model Coverage: 0.0
ReadDataDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1603832055, 1911162924 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
ReadDataDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 5 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
ReadDataDelayCov BeatDelay Coverage Model Coverage: 0.0
ReadDataDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1024899620, 41944993 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
ReadDataDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 0 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteAddressDelayCov BurstLength Coverage Model Coverage: 100.0
WriteAddressDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1170277353, 1510285710 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteAddressDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 31 | 1 | 3100.0 | |
Total Percent Coverage: 100.0 |
WriteAddressDelayCov BurstDelay Coverage Model Coverage: 100.0
WriteAddressDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 572323863, 322647680 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteAddressDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 5 | 31 | 1 | 3100.0 | |
Total Percent Coverage: 100.0 |
WriteAddressDelayCov BeatDelay Coverage Model Coverage: 100.0
WriteAddressDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1506195398, 562308689 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteAddressDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 0 | 129 | 1 | 12900.0 | |
Total Percent Coverage: 100.0 |
WriteDataDelayCov BurstLength Coverage Model Coverage: 100.0
WriteDataDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 896287029, 1206444957 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteDataDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 26 | 1 | 2600.0 | |
Total Percent Coverage: 100.0 |
WriteDataDelayCov BurstDelay Coverage Model Coverage: 100.0
WriteDataDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1462194706, 886079329 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteDataDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 5 | 26 | 1 | 2600.0 | |
Total Percent Coverage: 100.0 |
WriteDataDelayCov BeatDelay Coverage Model Coverage: 100.0
WriteDataDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 431158824, 76245666 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteDataDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 0 | 134 | 1 | 13400.0 | |
Total Percent Coverage: 100.0 |
WriteResponseDelayCov BurstLength Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1935614252, 1231610140 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteResponseDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteResponseDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 628491352, 1519532790 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteResponseDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteResponseDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1682240380, 1538165535 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteResponseDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 | 0 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
ReadAddressDelayCov BurstLength Coverage Model Coverage: 100.0
ReadAddressDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 166416498, 46514375 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadAddressDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 26 | 1 | 2600.0 | |
Total Percent Coverage: 100.0 |
ReadAddressDelayCov BurstDelay Coverage Model Coverage: 100.0
ReadAddressDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1164093329, 349948709 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadAddressDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 5 | 26 | 1 | 2600.0 | |
Total Percent Coverage: 100.0 |
ReadAddressDelayCov BeatDelay Coverage Model Coverage: 100.0
ReadAddressDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1590100984, 674388727 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadAddressDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 0 | 134 | 1 | 13400.0 | |
Total Percent Coverage: 100.0 |
ReadDataDelayCov BurstLength Coverage Model Coverage: 100.0
ReadDataDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 469555723, 956988202 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadDataDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 56 | 1 | 5600.0 | |
Total Percent Coverage: 100.0 |
ReadDataDelayCov BurstDelay Coverage Model Coverage: 100.0
ReadDataDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 2093883914, 1824743585 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadDataDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 to 1 | 2 to 5 | 56 | 1 | 5600.0 | |
Total Percent Coverage: 100.0 |
ReadDataDelayCov BeatDelay Coverage Model Coverage: 100.0
ReadDataDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1557672355, 1156293039 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadDataDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 | 0 | 264 | 1 | 26400.0 | |
Total Percent Coverage: 100.0 |
TbAxi4_ManagerRandomTiming1 Scoreboard Report for Scoreboard_slv
Name | ParentName | ItemCount | ErrorCount | ItemsChecked | ItemsPopped | ItemsDropped | FifoCount |
---|---|---|---|---|---|---|---|
WriteAddressFIFO | subordinate_1 | 160 | 0 | 0 | 160 | 0 | 0 |
WriteDataFifo | subordinate_1 | 160 | 0 | 0 | 160 | 0 | 0 |
WriteResponseFifo | subordinate_1 | 160 | 0 | 0 | 160 | 0 | 0 |
ReadAddressFifo | subordinate_1 | 160 | 0 | 0 | 160 | 0 | 0 |
ReadDataFifo | subordinate_1 | 160 | 0 | 0 | 160 | 0 | 0 |
WriteResponse Scoreboard | manager_1 | 160 | 0 | 160 | 160 | 0 | 0 |
ReadResponse Scoreboard | manager_1 | 160 | 0 | 160 | 160 | 0 | 0 |
WriteAddressFIFO | manager_1 | 160 | 0 | 0 | 160 | 0 | 0 |
WriteDataFifo | manager_1 | 160 | 0 | 0 | 160 | 0 | 0 |
ReadAddressFifo | manager_1 | 160 | 0 | 0 | 160 | 0 | 0 |
ReadAddressTransactionFifo | manager_1 | 160 | 0 | 0 | 160 | 0 | 0 |
ReadDataFifo | manager_1 | 160 | 0 | 0 | 160 | 0 | 0 |