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TbAxi4_ManagerSubordinateRandomTiming1 Alert Report
TbAxi4_ManagerSubordinateRandomTiming1 Alert Settings
Setting | Value | Description | |
---|---|---|---|
FailOnWarning | true | If true, warnings are a test error | |
FailOnDisabledErrors | true | If true, Disabled Alert Counts are a test error | |
FailOnRequirementErrors | true | If true, Requirements Errors are a test error | |
External | Failures | 0 | Added to Alert Counts in determine total errors |
Errors | 0 | ||
Warnings | 0 | ||
Expected | Failures | 0 | Subtracted from Alert Counts in determine total errors |
Errors | 0 | ||
Warnings | 0 |
TbAxi4_ManagerSubordinateRandomTiming1 Alert Results
Name | Status | Checks | Requirements | Alert Counts | Disabled Alert Counts | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Total | Passed | Failed | Goal | Passed | Failures | Errors | Warnings | Failures | Errors | Warnings | ||
TbAxi4_ManagerSubordinateRandomTiming1 | PASSED | 192 | 192 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Default | PASSED | 96 | 96 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
OSVVM | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
subordinate_1 | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Protocol Error | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Data Check | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
manager_1 | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Protocol Error | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Data Check | PASSED | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
No response | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
WriteResponse Scoreboard | PASSED | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
ReadResponse Scoreboard | PASSED | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
TbAxi4_ManagerSubordinateRandomTiming1 Coverage Report
Total Coverage: 100.00
WriteAddressDelayCov BurstLength Coverage Model Coverage: 100.0
WriteAddressDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 684691607, 883708446 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteAddressDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 4 | 11 | 1 | 1100.0 | |
Total Percent Coverage: 100.0 |
WriteAddressDelayCov BurstDelay Coverage Model Coverage: 100.0
WriteAddressDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 293930064, 234565500 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteAddressDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 to 1 | 2 to 5 | 11 | 1 | 1100.0 | |
Total Percent Coverage: 100.0 |
WriteAddressDelayCov BeatDelay Coverage Model Coverage: 100.0
WriteAddressDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1146139428, 1532954790 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteAddressDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 | 0 | 22 | 1 | 2200.0 | |
Total Percent Coverage: 100.0 |
WriteDataDelayCov BurstLength Coverage Model Coverage: 100.0
WriteDataDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 2128422036, 1036273574 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteDataDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 5 | 1 | 500.0 | |
Total Percent Coverage: 100.0 |
WriteDataDelayCov BurstDelay Coverage Model Coverage: 100.0
WriteDataDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 792345798, 395143149 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteDataDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 to 1 | 2 to 5 | 5 | 1 | 500.0 | |
Total Percent Coverage: 100.0 |
WriteDataDelayCov BeatDelay Coverage Model Coverage: 100.0
WriteDataDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 426841876, 1682243781 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteDataDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 | 0 | 28 | 1 | 2800.0 | |
Total Percent Coverage: 100.0 |
WriteResponseDelayCov BurstLength Coverage Model Coverage: 100.0
WriteResponseDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 740556423, 1008053622 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteResponseDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 6 | 1 | 600.0 | |
Total Percent Coverage: 100.0 |
WriteResponseDelayCov BurstDelay Coverage Model Coverage: 100.0
WriteResponseDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1090183749, 83551606 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteResponseDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 5 | 6 | 1 | 600.0 | |
Total Percent Coverage: 100.0 |
WriteResponseDelayCov BeatDelay Coverage Model Coverage: 100.0
WriteResponseDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1507060738, 1586916029 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteResponseDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 0 | 26 | 1 | 2600.0 | |
Total Percent Coverage: 100.0 |
ReadAddressDelayCov BurstLength Coverage Model Coverage: 100.0
ReadAddressDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 684691607, 1380341666 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadAddressDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 4 | 11 | 1 | 1100.0 | |
Total Percent Coverage: 100.0 |
ReadAddressDelayCov BurstDelay Coverage Model Coverage: 100.0
ReadAddressDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 119528654, 51466679 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadAddressDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 to 1 | 2 to 5 | 11 | 1 | 1100.0 | |
Total Percent Coverage: 100.0 |
ReadAddressDelayCov BeatDelay Coverage Model Coverage: 100.0
ReadAddressDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1146139428, 777748449 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadAddressDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 | 0 | 22 | 1 | 2200.0 | |
Total Percent Coverage: 100.0 |
ReadDataDelayCov BurstLength Coverage Model Coverage: 100.0
ReadDataDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 362439022, 2007298089 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadDataDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 5 | 1 | 500.0 | |
Total Percent Coverage: 100.0 |
ReadDataDelayCov BurstDelay Coverage Model Coverage: 100.0
ReadDataDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1858474827, 303084166 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadDataDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 5 | 5 | 1 | 500.0 | |
Total Percent Coverage: 100.0 |
ReadDataDelayCov BeatDelay Coverage Model Coverage: 100.0
ReadDataDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 878305371, 1087941120 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadDataDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 0 | 27 | 1 | 2700.0 | |
Total Percent Coverage: 100.0 |
WriteAddressDelayCov BurstLength Coverage Model Coverage: 100.0
WriteAddressDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 367261985, 965022672 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteAddressDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 5 | 1 | 500.0 | |
Total Percent Coverage: 100.0 |
WriteAddressDelayCov BurstDelay Coverage Model Coverage: 100.0
WriteAddressDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1762331630, 738734082 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteAddressDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 5 | 5 | 1 | 500.0 | |
Total Percent Coverage: 100.0 |
WriteAddressDelayCov BeatDelay Coverage Model Coverage: 100.0
WriteAddressDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 210786017, 1327788119 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteAddressDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 0 | 27 | 1 | 2700.0 | |
Total Percent Coverage: 100.0 |
WriteDataDelayCov BurstLength Coverage Model Coverage: 100.0
WriteDataDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1092135827, 18347283 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteDataDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 7 | 1 | 700.0 | |
Total Percent Coverage: 100.0 |
WriteDataDelayCov BurstDelay Coverage Model Coverage: 100.0
WriteDataDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1644481206, 835161482 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteDataDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 5 | 7 | 1 | 700.0 | |
Total Percent Coverage: 100.0 |
WriteDataDelayCov BeatDelay Coverage Model Coverage: 100.0
WriteDataDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1802919924, 346259646 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
WriteDataDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 0 | 25 | 1 | 2500.0 | |
Total Percent Coverage: 100.0 |
WriteResponseDelayCov BurstLength Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1935614252, 1231610140 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteResponseDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteResponseDelayCov BurstDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 628491352, 1519532790 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteResponseDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 to 1 | 2 to 5 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
WriteResponseDelayCov BeatDelay Coverage Model Coverage: 0.0
WriteResponseDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1682240380, 1538165535 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 0 |
TotalCovGoal | 1 |
WriteResponseDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 | 0 | 0 | 1 | 0.0 | |
Total Percent Coverage: 0.0 |
ReadAddressDelayCov BurstLength Coverage Model Coverage: 100.0
ReadAddressDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1252668943, 1325923108 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadAddressDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 4 | 1 | 400.0 | |
Total Percent Coverage: 100.0 |
ReadAddressDelayCov BurstDelay Coverage Model Coverage: 100.0
ReadAddressDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 654936549, 686219379 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadAddressDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 5 | 4 | 1 | 400.0 | |
Total Percent Coverage: 100.0 |
ReadAddressDelayCov BeatDelay Coverage Model Coverage: 100.0
ReadAddressDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1653012755, 689051489 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadAddressDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 0 | 28 | 1 | 2800.0 | |
Total Percent Coverage: 100.0 |
ReadDataDelayCov BurstLength Coverage Model Coverage: 100.0
ReadDataDelayCov BurstLength Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 477521543, 748446194 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadDataDelayCov BurstLength Coverage Bins
Name | Type | Bin1 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|
COUNT | 2 to 10 | 10 | 1 | 1000.0 | |
Total Percent Coverage: 100.0 |
ReadDataDelayCov BurstDelay Coverage Model Coverage: 100.0
ReadDataDelayCov BurstDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1499602811, 1367637731 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadDataDelayCov BurstDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 to 1 | 2 to 5 | 10 | 1 | 1000.0 | |
Total Percent Coverage: 100.0 |
ReadDataDelayCov BeatDelay Coverage Model Coverage: 100.0
ReadDataDelayCov BeatDelay Coverage Settings
Settings | Value |
---|---|
CovWeight | 0 |
Goal | 100.0 |
WeightMode | REMAIN |
Seeds | 1300946199, 141114146 |
CountMode | COUNT_FIRST |
IllegalMode | ILLEGAL_ON |
Threshold | 45.0 |
ThresholdEnable | FALSE |
TotalCovCount | 1 |
TotalCovGoal | 1 |
ReadDataDelayCov BeatDelay Coverage Bins
Name | Type | Bin1 | Bin2 | Count | AtLeast | Percent Coverage |
---|---|---|---|---|---|---|
COUNT | 0 | 0 | 54 | 1 | 5400.0 | |
Total Percent Coverage: 100.0 |
TbAxi4_ManagerSubordinateRandomTiming1 Scoreboard Report for Scoreboard_slv
Name | ParentName | ItemCount | ErrorCount | ItemsChecked | ItemsPopped | ItemsDropped | FifoCount |
---|---|---|---|---|---|---|---|
WriteAddressFIFO | subordinate_1 | 32 | 0 | 0 | 32 | 0 | 0 |
WriteDataFifo | subordinate_1 | 32 | 0 | 0 | 32 | 0 | 0 |
WriteTransactionFifo | subordinate_1 | 0 | 0 | 0 | 0 | 0 | 0 |
WriteResponseFifo | subordinate_1 | 32 | 0 | 0 | 32 | 0 | 0 |
ReadAddressFifo | subordinate_1 | 32 | 0 | 0 | 32 | 0 | 0 |
ReadAddressTransactionFifo | subordinate_1 | 32 | 0 | 0 | 32 | 0 | 0 |
ReadDataFifo | subordinate_1 | 32 | 0 | 0 | 32 | 0 | 0 |
WriteResponse Scoreboard | manager_1 | 32 | 0 | 32 | 32 | 0 | 0 |
ReadResponse Scoreboard | manager_1 | 32 | 0 | 32 | 32 | 0 | 0 |
WriteAddressFIFO | manager_1 | 32 | 0 | 0 | 32 | 0 | 0 |
WriteDataFifo | manager_1 | 32 | 0 | 0 | 32 | 0 | 0 |
ReadAddressFifo | manager_1 | 32 | 0 | 0 | 32 | 0 | 0 |
ReadAddressTransactionFifo | manager_1 | 32 | 0 | 0 | 32 | 0 | 0 |
ReadDataFifo | manager_1 | 32 | 0 | 0 | 32 | 0 | 0 |