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Open Source VHDL Verification Methodology (OSVVM)

Open Source VHDL Verification Methodology (OSVVM) provides utility and model libraries that simplify your FPGA and ASIC verification tasks. Using these libraries you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC.

OSVVM is the #1 VHDL Verification Methodology

According to the 2018 Wilson Verification Survey, OSVVM is the:

  • #1 VHDL Verification Methodology
  • #1 FPGA Verification Methodology in Europe (ahead of SystemVerilog + UVM)

The OSVVM Utility Library

The OSVVM utility library offers the same capabilities as those provided by other verification languages (such as SystemVerilog and UVM):

  • Transaction-Level Modeling
  • Constrained Random test generation
  • Functional Coverage with hooks for UCIS coverage database integration
  • Intelligent Coverage Random test generation
  • Utilities for testbench process synchronization generation
  • Utilities for clock and reset generation
  • Transcript files
  • Error logging and reporting - Alerts and Affirmations
  • Message filtering - Logs
  • Scoreboards and FIFOs (data structures for verification)
  • Memory models

Download the OSVVM Utility library using git:
git clone https://github.com/OSVVM/OSVVM.git

The OSVVM Model Library

The OSVVM model library is a growing set of models commonly used for FPGA and ASIC verification.
The library currently contains the following repositories:

  • Verification IP
    • Repository that includes all of the OSVVM model library as submodules.
    • Download the entire OSVVM model library using git clone with the “–recursive” flag:
      git clone --recursive https://github.com/OSVVM/VerificationIP.git
    • Note submodules are not included in the GitHub zip files
  • AXI4 Lite
    • Master
    • Slave transactor model
  • AXI Stream
    • Master
    • Slave
  • UART
    • Transmitter (aka master) - with error injection
    • Receiver (aka slave) - with error injection
  • OSVVM Common - Required
    • Shared transcript interfaces
  • OSVVM Scripts
    • Recommended. Script layer on top of tcl
    • Common simulator compilation and execution methodology

We use the word models as short hand for Transaction Based Models (TBM). They are simply an entity and architecture coded in an effective manner for verification. Some use other terminology such as VHDL verification components (VVC) - these are the same thing. Historically we used Bus Functional Models (BFM). However, recently we abandoned BFM due to others using BFM to refer to their own lesser capable subprogram based approach.

OSVVM models use records for the transaction interfaces, so connecting them to your testbench is simple - connect only a single signal.

Testbenches are in the Git repository, so you can run a simulation and see a live example of how to use the models.