Structured Testbench Framework¶

Some methodologies (or frameworks) are so complex that you need a script to create initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their “Lite” or “Easy” approach.

OSVVM is simple enough to use on small blocks and powerful enough to use on large, complex chips or systems. This allows us to use the same style of framework for RTL, Core, and Chip level verification - which in turn facilitates re-use of verification components and test cases. OSVVM has added the abstractions needed to make our verification component based approach as easy as the “Lite” approach of other methodologies.

SynthWorks has been using this framework for 25+ years in our training classes and consulting work. During that time, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort spent.

When we examine OSVVM’s framework in detail, we see that it has many similar elements to SystemVerilog + UVM. However, one thing not present is OO language constructs. Instead OSVVM uses ordinary VHDL constructs, such as structural and behavioral code. This makes it readily accessible to both verfication and RTL engineers.

Going Further¶

Read the following documents for more information on OSVVM’s Structured Testbench Framework.

Document	User Guide
OSVVM’s Structured Testbench Framework	UG
OSVVM’s Verification Component Developer’s Guide	UG
OSVVM’s Test Writers User Guide	UG
OSVVM’s Address Bus Model Independent Transactions Users Guide	UG
OSVVM’s Stream Model Independent Transactions Users Guide	UG

Related publications and webinars

Publications and Webinars	Event
OSVVM Leading Edge Verification for the VHDL Community	Part 1 of Better FPGA Verification with VHDL, With Aldec May 2022
Faster than Lite Verification Component Development with OSVVM	Part 2 of Better FPGA Verification with VHDL, With Aldec June 2022
OSVVM’s Test Reports and Simulator Independent Scripting	Part 3 of Better FPGA Verification with VHDL, With Aldec June 2022
Advances in OSVVM’s Verification Data Structures	Part 4 of Better FPGA Verification with VHDL, With Aldec June 2022
OSVVM: Leading Edge Verification for the VHDL Community	DVClub Europe April 2022