VHDL Utility Library

VHDL Utility Library

The OSVVM Utility Library implements the advanced verification capabilities found in other verification languages (such as SystemVerilog and UVM) as packages. The list below lists out many of the OSVVM features and the package in which they are implemented.

• Constrained Random test generation (RandomPkg)

• Functional Coverage with hooks for UCIS coverage database integration (CoveragePkg)

• Intelligent Coverage Random test generation (CoveragePkg)

• Utilities for testbench process synchronization generation (TbUtilPkg)

• Utilities for clock and reset generation (TbUtilPkg)

• Transcript files (TranscriptPkg)

• Error logging and reporting - Alerts and Affirmations (AlertLogPkg)

• Message filtering - Logs (AlertLogPkg)

• Scoreboards and FIFOs (data structures for verification) (ScoreboardGenericPkg)

• HTML and JUnit XML test reporting (ReportPkg, AlertLogPkg, CoveragePkg, ScoreboardGenericPkg)

• Memory models (MemoryPkg)

• Transaction-Level Modeling Support (TbUtilPkg, ResolutionPkg)

Through the years, the packages have been updated many times. Now, all of the packages that create data structures (AlertLogPkg, CoveragePkg, ScoreboardGenericPkg, and MemoryPkg) use singleton data structures. Usage of singletons simplifies API to an ordinary call interface - ie: no more shared variables and protected types.

Going Further

Read the following documents for more information on OSVVM’s VHDL Utility Library.

Document	User Guide	Quick Reference
OSVVM Test Writer’s User Guide - a general overview to usage	UG	None
AlertLogPkg	UG	QR
TranscriptPkg	UG	QR
RandomPkg	UG	QR
CoveragePkg	UG	QR
ScoreboardGenericPkg	UG	QR
TbUtilPkg	UG	QR
MemoryPkg	UG	None
TextUtilPkg	UG	None

Related publications and webinars

Publications and Webinars	Event
OSVVM Leading Edge Verification for the VHDL Community	Part 1 of Better FPGA Verification with VHDL, With Aldec May 2022
Faster than Lite Verification Component Development with OSVVM	Part 2 of Better FPGA Verification with VHDL, With Aldec June 2022
OSVVM’s Test Reports and Simulator Independent Scripting	Part 3 of Better FPGA Verification with VHDL, With Aldec June 2022
Advances in OSVVM’s Verification Data Structures	Part 4 of Better FPGA Verification with VHDL, With Aldec June 2022
OSVVM: Leading Edge Verification for the VHDL Community	DVClub Europe April 2022