TbUart_SingleProcess_1 Test Case Detailed Report



Available Reports
Alert Report
ScoreboardPkg_slv Report(s)
ScoreboardPkg_Uart Report(s)
Link to Simulation Results
SingleProcess_1.txt
sim_OsvvmDemo Build Summary



TbUart_SingleProcess_1 Alert Report

TbUart_SingleProcess_1 Alert Settings

Setting Value Description
FailOnWarning true If true, warnings are a test error
FailOnDisabledErrors true If true, Disabled Alert Counts are a test error
FailOnRequirementErrors true If true, Requirements Errors are a test error
External Failures 0 Added to Alert Counts in determine total errors
Errors 0
Warnings 0
Expected Failures 0 Subtracted from Alert Counts in determine total errors
Errors 0
Warnings 0

TbUart_SingleProcess_1 Alert Results

Name Status Checks Requirements Alert Counts Disabled Alert Counts
Total Passed Failed Goal Passed Failures Errors Warnings Failures Errors Warnings
TbUart_SingleProcess_1 PASSED 16 16 0 0 0 0 0 0 0 0 0
  Default PASSED 0 0 0 0 0 0 0 0 0 0 0
  OSVVM PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_16 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_16 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_15 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_15 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_14 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_14 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_13 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_13 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_12 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_12 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_11 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_11 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_10 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_10 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_9 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_9 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_8 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_8 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_7 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_7 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_6 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_6 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_5 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_5 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_4 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_4 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_3 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_3 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_2 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_2 PASSED 0 0 0 0 0 0 0 0 0 0 0
  UartRx_1 PASSED 1 1 0 0 0 0 0 0 0 0 0
  UartTx_1 PASSED 0 0 0 0 0 0 0 0 0 0 0




TbUart_SingleProcess_1 Scoreboard Report for Scoreboard_slv


Name ParentName ItemCount ErrorCount ItemsChecked ItemsPopped ItemsDropped FifoCount
ReceiveFifo UartRx_16 1 0 0 1 0 0
TransmitFifo UartTx_16 1 0 0 1 0 0
ReceiveFifo UartRx_15 1 0 0 1 0 0
TransmitFifo UartTx_15 1 0 0 1 0 0
ReceiveFifo UartRx_14 1 0 0 1 0 0
TransmitFifo UartTx_14 1 0 0 1 0 0
ReceiveFifo UartRx_13 1 0 0 1 0 0
TransmitFifo UartTx_13 1 0 0 1 0 0
ReceiveFifo UartRx_12 1 0 0 1 0 0
TransmitFifo UartTx_12 1 0 0 1 0 0
ReceiveFifo UartRx_11 1 0 0 1 0 0
TransmitFifo UartTx_11 1 0 0 1 0 0
ReceiveFifo UartRx_10 1 0 0 1 0 0
TransmitFifo UartTx_10 1 0 0 1 0 0
ReceiveFifo UartRx_9 1 0 0 1 0 0
TransmitFifo UartTx_9 1 0 0 1 0 0
ReceiveFifo UartRx_8 1 0 0 1 0 0
TransmitFifo UartTx_8 1 0 0 1 0 0
ReceiveFifo UartRx_7 1 0 0 1 0 0
TransmitFifo UartTx_7 1 0 0 1 0 0
ReceiveFifo UartRx_6 1 0 0 1 0 0
TransmitFifo UartTx_6 1 0 0 1 0 0
ReceiveFifo UartRx_5 1 0 0 1 0 0
TransmitFifo UartTx_5 1 0 0 1 0 0
ReceiveFifo UartRx_4 1 0 0 1 0 0
TransmitFifo UartTx_4 1 0 0 1 0 0
ReceiveFifo UartRx_3 1 0 0 1 0 0
TransmitFifo UartTx_3 1 0 0 1 0 0
ReceiveFifo UartRx_2 1 0 0 1 0 0
TransmitFifo UartTx_2 1 0 0 1 0 0
ReceiveFifo UartRx_1 1 0 0 1 0 0
TransmitFifo UartTx_1 1 0 0 1 0 0


TbUart_SingleProcess_1 Scoreboard Report for Scoreboard_Uart


Name ParentName ItemCount ErrorCount ItemsChecked ItemsPopped ItemsDropped FifoCount
OSVVM TbUart_SingleProcess_1 0 0 0 0 0 0