Available Reports |
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Alert Report |
ScoreboardPkg_int Report(s) |
ScoreboardPkg_slv Report(s) |
Link to Simulation Results |
Tb_xMii1.txt |
OsvvmLibraries_RunErrorTestsWithCoverage Build Summary |
Tb_xMii1 Alert Report
Tb_xMii1 Alert Settings
Setting | Value | Description | |
---|---|---|---|
FailOnWarning | true | If true, warnings are a test error | |
FailOnDisabledErrors | true | If true, Disabled Alert Counts are a test error | |
FailOnRequirementErrors | true | If true, Requirements Errors are a test error | |
External | Failures | 0 | Added to Alert Counts in determine total errors |
Errors | 0 | ||
Warnings | 0 | ||
Expected | Failures | 0 | Subtracted from Alert Counts in determine total errors |
Errors | 0 | ||
Warnings | 0 |
Tb_xMii1 Alert Results
Name | Status | Checks | Requirements | Alert Counts | Disabled Alert Counts | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Total | Passed | Failed | Goal | Passed | Failures | Errors | Warnings | Failures | Errors | Warnings | ||
Tb_xMii1 | PASSED | 2065 | 2065 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Default | PASSED | 17 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
OSVVM | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
xmiimac_1.Tx | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
xmiimac_1.Rx | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
xmiiphy_1.Tx | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
xmiiphy_1.Rx | PASSED | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Tb_xMii1 Scoreboard Report for Scoreboard_int
Name | ParentName | ItemCount | ErrorCount | ItemsChecked | ItemsPopped | ItemsDropped | FifoCount |
---|---|---|---|---|---|---|---|
MetaFifo | xmiimac_1.Tx | 32 | 0 | 0 | 32 | 0 | 0 |
MetaFifo | xmiimac_1.Rx | 36 | 0 | 0 | 9 | 0 | 27 |
MetaFifo | xmiiphy_1.Tx | 32 | 0 | 0 | 8 | 0 | 24 |
MetaFifo | xmiiphy_1.Rx | 36 | 0 | 0 | 36 | 0 | 0 |
Tb_xMii1 Scoreboard Report for Scoreboard_slv
Name | ParentName | ItemCount | ErrorCount | ItemsChecked | ItemsPopped | ItemsDropped | FifoCount |
---|---|---|---|---|---|---|---|
DataFifo | xmiimac_1.Tx | 4096 | 0 | 0 | 4096 | 0 | 0 |
DataFifo | xmiimac_1.Rx | 4096 | 0 | 0 | 1024 | 0 | 3072 |
DataFifo | xmiiphy_1.Tx | 4096 | 0 | 0 | 1024 | 0 | 3072 |
DataFifo | xmiiphy_1.Rx | 4096 | 0 | 0 | 4096 | 0 | 0 |
BurstFifo | xmiimac_1.Tx | 4096 | 0 | 0 | 4096 | 0 | 0 |
BurstFifo | xmiimac_1.Rx | 1024 | 0 | 1024 | 1024 | 0 | 0 |
BurstFifo | xmiiphy_1.Tx | 1024 | 0 | 1024 | 1024 | 0 | 0 |
BurstFifo | xmiiphy_1.Rx | 4096 | 0 | 0 | 4096 | 0 | 0 |